The lifetime, i.e. time between first use and failure, of semiconductor dies can be approximated by test structures. Electromigration (“EM”), i.e. the transport of atoms in metal due to the “electron wind” effect, can ultimately cause failure in semiconductor dies due to the formation of “voids”, i.e. open circuits, or “hillocks”, i.e. extrusions causing short circuits, in metal lines.
EM test structures simulate the failure of devices due to the effects of electromigration. The National Institute of Standards and Technology (“NIST”) has proposed a standard of 800 microns for EM test structure length. Conventional EM test structures comprise metal lines in a linear configuration having an EM test structure length of 800 microns. These conventional EM test structures are typically situated on scribe lines on a semiconductor wafer.
Disadvantageously, situating conventional EM test structures on scribe lines requires significant consumption of wafer area due to EM test structures having linear configurations and EM test structure lengths of 800 microns, which result in less wafer area for die fabrication, and which increase manufacturing costs. Moreover, conventional EM test structures lack the capability of rapidly detecting extrusions. Conventional EM test structures further lack the capability of performing effective isothermal testing, i.e. detecting voids formed due to the Joule heating effect. Accordingly, there exists a strong need in the art to overcome deficiencies of known test structures such as those described above.